7721 datasheet(379/577 Pages) RENESAS

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DMA CONTROLLER

13-100

13.9 DMA transfer time

7721 Group User’s Manual

(3)

Transfer of array state

In the following cases, the processing in an array state and the first 1-unit transfer are performed

sequentially. (Refer to “Figures 13.8.10 and 13.8.11.”)

• Array chain transfer mode: the first transfer of each block

• Link array chain transfer mode: the first transfer of each block

Right to use

bus

Array state

CPU

DMAC

CPU

Transfer

Transition

Fig. 13.9.3 Transfer of array state

Transition of the right to use bus from CPU to DMAC: 1 cycle

Array state:

The number of transfer parameters

× the number of reads of a transfer parameter × the number

of bus cycles for a read + 1 cycle (Refer to “Table 13.9.1.”)

DMA transfer per 1-unit transfer:

• In 2-bus cycle transfer···Read cycle + Write cycle

(Add a value which satisfies the read/write conditions. Refer to “Table 13.4.1.”)

• In 1-bus cycle transfer···Refer to “Table 13.4.5.”

Transition of the right to use bus from DMAC to CPU: 1 cycle

[Example]

Link array chain transfer mode, external data bus width = 16 bits, 2-bus cycle transfer, transfer unit

=16 bits, and under the following conditions:

• Transfer source: address direction = forward, start address of data = even, with Wait

• Transfer destination: address direction = backward, start address of data =odd, with Wait

+ + + = 1 + 25 + (3 + 4) + 1 = 34 cycles

Table 13.9.1 Time required for processing in array state

External data

bus width

Mode

Transfer method

Array

chain

transfer mode

16 bits

(Including internal bus)

8 bits

16 bits

(Including internal bus)

Link array chain

transfer mode

2-bus cycle transfer

1-bus cycle transfer

2-bus cycle transfer

1-bus cycle transfer

2-bus cycle transfer

1-bus cycle transfer

2-bus cycle transfer

1-bus cycle transfer

× 2 × 3 + 1 = 19

× 2 × 3 + 1 = 13

× 4 × 3 + 1 = 37

× 4 × 3 + 1 = 25

× 2 × 3 + 1 = 25

× 2 × 3 + 1 = 19

× 4 × 3 + 1 = 49

× 4 × 3 + 1 = 37

Time required for

processing in array state

(Unit:

φ cycle)

Number of reads of

a transfer parameter

Number of transfer

parameters

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