7721 datasheet(375/577 Pages) RENESAS

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DMA CONTROLLER

13-96

13.8 Link array chain transfer mode

7721 Group User’s Manual

ALE

R/W

A0–A7

A8/D8–A15/D15

A16/D0–A23/D7

Bus request sampling

DMAACKi

ST1, ST0

(sa2+n-2)L

1, 0 (DMAC)

1-unit transfer

DataL

PCL

PCH

PCL

PCH

(da2+n-2)L

DataH

(sa2+n-2)M

(sa2+n-2)H

(da2+n-2)M

(da2+n-2)H

1, 1 (CPU)

(sa2+n)L

(sa2+n)M

(sa2+n)H

Terminate processing

q Last transfer of last block

At the last term for processing the last block in the single, array chain, and link array chain

transfer modes, 1-unit transfer and terminate processing are subsequently performed with

one DMAi request.

Transition of

right to use bus

q The above figure is the example of the last term for processing the second block in “Figure 13.8.9.”

q The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling

signal is “H,” and is accepted.

Transition of

right to use bus

Fig. 13.8.14 Timing diagram of cycle-steal transfer mode (5)

Data

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