7721 datasheet(374/577 Pages) RENESAS

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DMA CONTROLLER

13.8 Link array chain transfer mode

13-95

7721 Group User‘s Manual

Fig. 13.8.13 Timing diagram of cycle-steal transfer mode (4)

(sa1+m–2)L

1, 0 (DMAC)

1-unit transfer

DataL

PCL

PCH

PCL

PCH

(da1+m–2)L

DataH

(sa1+m-2)M

(sa1+m-2)H

(da1+m-2)M

(da1+m-2)H

1, 1 (CPU)

Transition of right

to use bus

(sa1+m)L

(sa1+m)M

(sa1+m)H

ALE

R/W

A0–A7

A8/D8–A15/D15

A16/D0–A23/D7

Bus request sampling

DMAACKi

ST1, ST0

q The above figure is the example of the last term for processing the first block in “Figure 13.8.9.”

q The Bus request caused by DRAM refresh, Hold, or DMA is sampled while the bus request sampling signal is “H,” and

is accepted.

Transition of right

to use bus

q Last transfer of each block

At the last term (except for the last block) for processing of each block in the repeat, array chain,

and link array chain transfer modes, 1-unit transfer is performed with one DMAi request, and the

right to use bus is relinquished after 3 cycles of

Data

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