7721 datasheet(367/577 Pages) RENESAS

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DMA CONTROLLER

13-88

13.8 Link array chain transfer mode

7721 Group User’s Manual

Note: When TC pin validity bit is “1”

First of each block ?

SARi

← Transfer parameter (Note)

(Transfer source’s transfer start address)

DARi

← Transfer parameter (Note)

(Transfer destination’s transfer start address)

TCRi

← Transfer parameter

(Byte number of transfer data)

SARi latch

← Transfer parameter (Start address of

next transfer parameter memory)

First

On and after

second

Transfer

completion of all blocks ?

SARi latch = 0 ?

Y. Completion

“L” output (Note)

DMAi interrupt request bit

← 1

DMAi enable bit

← 0

DMAi request bit

← 0

1-unit transfer

Transfer completion

of 1 block ?

(Only in cycle-steal transfer mode)

(Refer to section “13.4 Operation.”)

DMAi request bit

← 0

(Only in burst transfer mode (edge sense))

DMAi request bit ?

Burst·Level·H

Cycle-steal·No request

Burst·Edge

: In burst transfer mode (edge sense)

Burst·Level·L

: In burst transfer mode (level sense) with DMAREQi pin’s input level = L

Burst·Level·H

: In burst transfer mode (level sense) with DMAREQi pin’s input level = H

Cycle-steal·Requested

: In cycle-steal transfer mode with any request of DMA0–3

Cycle-steal·No request

: In cycle-steal transfer mode with no request of DMA0–3

SARi latch indicates the start address of the transfer parameter memory of the next block.

Note: The above figure applies when 2-bus cycle transfer is performed.

When data is transferred from memory to I/O in 1-bus cycle transfer, there is no “DARi

← Transfer parameter.”

When data is transferred from I/O to memory in 1-bus cycle transfer, there is no “SARi

← Transfer parameter.”

Burst·Edge

Burst·Level·L

Cycle-steal·Requested

Burst·Level·H

Cycle-steal·No request

DMAi request bit ?

Burst·Edge

Burst·Level·L

Cycle-steal·Requested

Fig. 13.8.6 Operation flowchart of link array chain transfer mode

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