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7721 Datasheet(PDF) 399 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 399 Page - Renesas Technology Corp |
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399 / 577 page  WATCHDOG TIMER 7721 Group User’s Manual 15–4 15.2 Operation description 15.2 Operation description 15.2.1 Basic operation Watchdog timer starts counting down from “FFF16.” When the Watchdog timer’s most significant bit becomes “0” (counted 2048 times), a watchdog timer interrupt request occurs. (Refer to “Table 15.2.1.”) When the interrupt request occurs at above , a value “FFF16” is set to Watchdog timer. The watchdog timer interrupt is a non-maskable interrupt. When the watchdog timer interrupt request is accepted, the processor interrupt priority level (IPL) is set to “1112.” Table 15.2.1 Occurrence interval of watchdog timer interrupt request f(XIN) = 25 MHz Occurrence interval 41.94 ms 2.62 ms Count source f512 f32 Watchdog timer frequency select bit 0 1 |
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