7721 datasheet(402/577 Pages) RENESAS

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WATCHDOG TIMER

7721 Group User’s Manual

15–7

15.3 Precautions for Watchdog timer

1. When dummy data is written to address 6016 with the 16-bit data length, writing to address 6116 is

simultaneously performed. Accordingly, when the user does not want to change a value of the watchdog

timer frequency select bit (bit 0 at address 6116), write the previous value to the bit simultaneously with

writing to address 6016.

2. When the STP instruction is executed, Watchdog timer stops. (Refer to section “5.3 Stop mode.”)

3. Watchdog timer stops during DRAM refresh, hold state, and DMAC operation. (For Watchdog timer’s

structure, refer to “Figure 15.1.1.”) Accordingly, when a bus request is changed in the period which is

shorter than 1 cycle of the count source (Note), Watchdog timer’s count may gain. (Refer to “Figure

15.3.1.”)

Note: f32 or f512, which is selected by the watchdog timer frequency select bit

Fig. 15.3.1 Count source for Watchdog timer

f32 or f512

Bus request

Count source which is actually

counted by Watchdog timer

In case the bus request is

changed in a period which is

shorter than 1 cycle of f32 or f512

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