7721 datasheet(405/577 Pages) RENESAS

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APPLICATION

7721 Group User’s Manual

16–2

16.1 Memory connection

This chapter describes application. Application shown here is just examples. The user shall modify them

according to the actual application and test them.

16.1 Memory connection

This section shows examples for memory and I/O connection. Refer to “CHAPTER 3. CONNECTION WITH

EXTERNAL DEVICES” for details about the functions and operations of used pins when connecting a

memory or I/O. Refer to section “Appendix 11. Electrical characteristics” for timing requirements of the

microcomputer.

16.1.1 Memory connection model

For the M37721, the level of the external data bus width select signal makes it possible to select the

memory connection model from the four models listed in Table 16.1.1.

(1)

Minimum model

This is a connection model of which external data bus width is 8 bits and access space is expanded

up to 64 Kbytes. It is unnecessary to connect the address latch externally, so this model gives priority

to cost and is most suitable when connecting the memory of which data bus width is 8 bits.

(2)

Medium model A

This is a connection model of which external data bus width is 8 bits and access space is expanded

up to 16 Mbytes. In this model, the high-order 8 bits of the external address bus (A16 to A23) are

multiplexed with the external data bus. Therefore, an n-bit (n

≤ 8) address latch is required for

latching n bits of the address in A16 to A23.

(3)

Medium model B

This is a connection model of which external data bus width is 16 bits and access space is expanded

up to 64 Kbytes. This model gives priority to rate performance. In this model, the middle-order 8 bits

of the external address bus (A8 to A15) are multiplexed with the external data bus. Therefore, an 8-

bit address latch is required for latching A8 to A15.

(4)

Maximum model

This is a connection model of which external data bus width is 16 bits and access space is expanded

up to 16 Mbytes. In this model, the high- and middle-order 16 bits of the external address bus (A8

to A23) are multiplexed with the external data bus. Therefore, an 8-bit address latch for latching A8

to A15 and an n-bit (n

≤ 8) address latch for latching n bits of A16 to A23 are required.

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