7721 datasheet(409/577 Pages) RENESAS

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7721 Group User’s Manual

16–6

16.1 Memory connection

q Timing for reading data from DRAM

Fig. 16.1.3 Timing for reading data from DRAM

____

CAS access time : tCAC

≤ tw(EL) – td(E-CASL) – tsu(DL/DH-E)

____

RAS access time : tRAC

≤ tw(EL) – td(E-RASL) – tsu(DL/DH-E)

Column address access time : tAA

≤ tw(EL) – td(E-CA) – tsu(DL/DH-E)

___

OE access time : tOEA

≤ tw(EL) – tsu(DL/DH-E)

Table 16.1.3 lists the calculation formula and value for each parameter in Figure 16.1.3. Figure

16.1.4 shows the relationship between tCAC, tRAC, tAA and f(XIN).

tw(EL)

td(E-RASL)

td(E-CA)

Address

tOEA

tRAC

tCLZ

tCAC

tOEZ V2

td(E-CASL)

Row address

Column address

RAS

CAS

Address output

(MA0–MA7)

Address output and Data I/O

tAA

tsu(DL/DH-E)

A8/D8–A15/D15

A16/D0–A23/D7

DRAM data output

Data

: Specifications of the M37721

(The others are specifications of DRAM.)

V1 This applies when the external data bus has a width of 16 bits (BYTE = “L”).

V2 If one of DRAM’s specifications is greater than tpzx(E–DLZ/DHZ) , there is a possibility that

the tail of data collides with the head of address.

→ Refer to section “(3) Precautions on

memory connection.”

Note: tpzx(E-DLZ/DHZ) : tpzx(E-DLZ) or tpzx(E-DHZ)

tsu(DL/DH-E) : tsu(DL-E) or tsu(DH-E)

DRAM output enable signal

(Read signal)

tpzx(E–DLZ/DHZ)

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