7721 datasheet(411/577 Pages) RENESAS

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APPLICATION

7721 Group User’s Manual

16–8

16.1 Memory connection

(2)

Timing for writing data

When writing data, the output data is stabilized when an interval of td(E-DLQ/DHQ) has passed after the

falling edge of the E signal. This data is continuously output until when an interval of th(E-DLQ/DHQ) has

passed after the rising edge of the E signal.

Data to be written to an external memory must satisfy the data set up time (tsu(D)) (for DRAM, the data

hold time (tDH)) of the external memory.

The following are described below:

•Timing for writing data to flash memory, SRAM, and DRAM

•Calculation formulas which are for tsu(D) and tDH to be satisfied

q Timing for writing data to flash memory and SRAM

tsu(D)

th(D)

Address

Data

External memory

chip select signals

CE, S

tw(EL)

th(E-DLQ/DHQ)

(The others are specifications of external memory.)

: Specifications of the M37721

V This applies when the external data bus has a width of 16 bits (BYTE = “L”).

td(E–DLQ/DHQ)

A8/D8–A15/D15

A16/D0–A23/D7

Address output and Data input

External memory

write signal

Address

Fig. 16.1.5 Timing for writing data to flash memory and SRAM

Data setup time : tsu(D)

≤ tw(EL) – td(E-DLQ/DHQ)

Table 16.1.4 lists the calculation formulas and values for each parameter in Figure 16.1.5, Figure

16.1.6 shows the relationship between tsu(D) and f(XIN).

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