7721 datasheet(416/577 Pages) RENESAS

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APPLICATION

7721 Group User’s Manual

16–13

16.1 Memory connection

M37721

A8–A23

(D0–D15)

A0–A7

RDY

Address

decode

circuit

AC74

AC32

Data bus

CS1

CS2

Address bus

AC04

Validate Ready function

only for areas accessed by

CS2.

Circuit conditions : f(XIN)

≤ 15.7 MHz, no software Wait

V1 to V3 : Make sure that the sum of

propagation delay time is within

15 ns.

V3 to V5 : Make sure that the sum of

propagation delay time is within

72 ns.

Ready request is accepted at A .

Termination request for Ready state is accepted

at B .

A , B : Judgement timing of RDY pin’s input

level

td(E- 1)

CS2

RDY

tsu(RDY- 1)

AC32(tPHL)

Address

latch

circuit

: E (“L” level) stopped by Ready function

V The condition satisfy tsu(RDY– 1)

≥ 55 ns is tc

≥ 63.5 ns. (This applies when AC32’s

propagation delay time is within 8.5 ns.)

Accordingly, when f(XIN)

≤ 15.7 MHz, this

circuit example satisfies tsu(RDY– 1)

≥ 55 ns.

Fig. 16.1.9 Example of using Ready function (no software Wait)

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