7721 datasheet(476/577 Pages) RENESAS

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APPENDIX

Appendix 3. Control registers

7721 Group User’s Manual

17–13

UARTi transmit/receive mode register

UARTi baud rate register

Bit

Bit name

At reset

Functions

b2 b1 b0

Serial I/O mode select bits

0 0 0 : Serial I/O disabled

(P8 functions as a programmable

I/O port.)

0 0 1 : Clock synchronous serial I/O

mode

0 1 0 : Do not select.

0 1 1 : Do not select.

1 0 0 : UART mode

(Transfer data length = 7 bits)

1 0 1 : UART mode

(Transfer data length = 8 bits)

1 1 0 : UART mode

(Transfer data length = 9 bits)

1 1 1 : Do not select.

Sleep select bit

(Valid in UART mode) (Note)

Parity enable bit

(Valid in UART mode) (Note)

Odd/Even parity select bit

(Valid in UART mode when

parity enable bit is “1”) (Note)

Stop bit length select bit

(Valid in UART mode) (Note)

Internal/External clock select bit

UART0 transmit/receive mode register (Address 3016)

UART1 transmit/receive mode register (Address 3816)

Note: Bits 4 to 6 are invalid in the clock synchronous serial I/O mode. (They may be either “0”

or “1.”) Additionally, fix bit 7 to “0.”

0 : Odd parity

1 : Even parity

0 : Parity disabled

1 : Parity enabled

0 : Sleep mode terminated (Invalid)

1 : Sleep mode selected

0 : Internal clock

1 : External clock

0 : One stop bit

1 : Two stop bits

UART0 baud rate register (Address 3116)

UART1 baud rate register (Address 3916)

Functions

Bit

At reset

7 to 0

Can be set to “0016” to “FF16.”

Assuming that the set value = n, BRGi

divides the count source frequency by (n + 1).

Undefined

Note: Writing to this register must be performed while the transmission/reception halts.

Use the LDM or STA instruction for writing to this register.

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