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7721 Datasheet(PDF) 537 Page - Renesas Technology Corp |
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7721 Datasheet(HTML) 537 Page - Renesas Technology Corp |
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537 / 577 page ![]() APPENDIX Appendix 9. 7721 Group Q & A 7721 Group User’s Manual 17–74 A In the wait mode, DRAM refresh function does not operate, but the watchdog timer, timer A, and timer B operate. Accordingly, DRAM can be refreshed by using these timers and ports. (1) Method using watchdog timer Return from the wait mode by the watchdog timer interrupt. Control ports P104, P105 by ____ ____ software and perform the CAS-before-RAS- refresh. Example 1: A case in 1024 refresh cycles, every 16.4 ms, f(XIN) = 16 MHz, watchdog timer count source = f32 •DRAM refresh is performed 256 times. This refresh is performed by every watchdog timer interrupt. (See flow chart .) Interval of watchdog timer interrupt f(XIN) 25 MHz 16 MHz f32 selected 2.621 ms 4.096 ms f512 selected 41.943 ms 65.536 ms (1/2) DRAM validity bit (bit 7 at address 6416) Bits 4, 5 of port P10 register (address 1616) ← “1” WIT instruction Wait mode completed ? N Y Wait mode DRAMC stopped Watchdog timer count source: f32 selected Ports P104, P105: “H” level output Note: By using 1 bit of RAM, judge whether this interrupt is for return from the wait mode or for refresh. 256 times ? N Y RTI Return to main routine ← “1” Bits 4, 5 of port P10 direction register (address 1816) ← “1” ← “0” Watchdog timer frequency select bit (bit 0 at address 6116) Main routine Flow chart Watchdog timer interrupt routine ← “0” Bit 4 of port P10 register (address 1616) ← “0” Bit 5 of port P10 register (address 1616) ← “1” Bit 4 of port P10 register (address 1616) ← “1” Bit 5 of port P10 register (address 1616) Port P105 (RAS) “H” level output Port P104 (CAS): “H” level output Port P105 (RAS): “L” level output Port P104 (CAS): “L” level output Port P105 (RAS): “H” level output |
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