7721 datasheet(539/577 Pages) RENESAS

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APPENDIX

Appendix 9. 7721 Group Q & A

7721 Group User’s Manual

17–76

DRAM

How is the program execution time affected when using DRAM ?

(1/2)

Rate occupied by DRAM refresh cycle during program execution time

Rate occupied by DRAM refresh cycle

f(XIN) = 25 MHz

2.6 %

0.3 %

f(XIN) = 16 MHz

4.2 %

0.5 %

Refresh interval

15.625

µs

(Case of 512 refresh cycles, every 8 ms)

125

µs

(Case of 512 refresh cycles, every 64 ms)

When the M37721 uses DRAM, the execution time is affected as follows:

•CPU stops and DRAM refresh cycle is inserted.

•1-bus cycle becomes 3

φ when accessing DRAM.

(1) Refresh method of the M37721’s DRAMC is the dispersion refresh and 5 cycles of

φ are

necessary for one refresh. The rate occupied by the DRAM refresh cycle during the program

execution time is described below.

(2) The comparison results of two sample programs’ execution times are listed below; one is for

the case where SRAM is used and the other is for the case where DRAM is used.

Use conditions : Execution program

Sample program B (See (2/2))

f(XIN)

16 MHz

External data bus width 16 bits

Refresh interval

µs

Memory used as work area

SRAM

DRAM (bank FF16)

Software wait valid area

Nothing

ROM and RAM

Nothing

ROM

Speed comparison

1.00

1.47

1.15

1.53

Execution time

3.4 ms

5.0 ms

3.9 ms

5.2 ms

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