7721 datasheet(538/577 Pages) RENESAS

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APPENDIX

7721 Group User’s Manual

17–75

Appendix 9. 7721 Group Q & A

DRAM, WIT instruction

(2) Method using timer A or timer B

Return from the wait mode by a timer A ( or timer B) interrupt every definite time. Control

____

ports P104, P105 by software and perform the CAS-before-RAS-refresh.

Example 2: A case in 512 refresh cycles, every 64 ms, f(XIN) = 25 MHz, timer A0 used

•DRAM refresh is performed 512 times by timer A0 interrupts. This interrupt

occurs every 64 ms. (See flow chart .)

(2/2)

Flow chart

Main routine

← “1”

Bits 4, 5 of port P10 direction

← “1”

Bits 4, 5 of port P10 register

(address 1616)

DRAM validity bit

(bit 7 at address 6416)

← “0”

Timer A0 mode

← “110000002”

Timer A0 register

(addresses 4716, 4616)

← 3124

Timer A0 interrupt

control register (address 7516)

← “XXXX00012”

Timer A0 count start

bit (bit 0 at address 4016)

← “1”

Interrupt enable flag I

← “0”

WIT instruction

Wait mode completed ?

Wait mode

Timer A0

interrupt routine

← “0”

Bit 4 of port P10 register

(address 1616)

← “0”

Bit 5 of port P10 register

(address 1616)

← “1”

Bit 4 of port P10 register

(address 1616)

← “1”

Bit 5 of port P10 register

(address 1616)

512 times ?

RTI

Return to main routine

Port P105 (RAS):

“H” level output

Port P104 (CAS):

“H” level output

Port P105 (RAS):

“L” level output

Port P104 (CAS):

“L” level output

Ports P104, P105:

“H” level output

DRAMC stopped

f512 counted

Timer value set:

One cycle = 64 ms

Interrupt priority level set:

Level 1 or more (Interrupt

enabled)

Timer A0 count started

Interrupt enabled

Note: By using 1 bit of RAM, judge

whether this interrupt is for return

from the wait mode or for refresh.

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