7721 datasheet(292/577 Pages) RENESAS

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7721 Group User’s Manual

13-13

DMA CONTROLLER

Mode

Maintains the transfer start address of the

source.

13.2 Block description

Single transfer mode Repeat transfer mode Array chain transfer

mode

SARi

DARi

Indicates the transfer source address of the data to be transferred next.

SARi

SARi latch

DARi

Indicates the transfer destination address of the data next to be transferred

DARi latch

Indicates the start address of the transfer

parameter memory of the next block.

Maintains the transfer start address of the

destination.

(Not used)

TCRi

Indicates the number of remaining bytes of the block under transfer.

TCRi

TCRi latch

Table 13.2.5 Functions of SARi, DARi, and TCRi

Maintains the byte number of the transfer

data.

Indicates the number

of remaining blocks.

(Not used)

Link array chain

transfer mode

(Not used) (Note)

Note: Any value other than 0 (00000116–FFFFFF16) must be written before DAM transfer.

13.2.7 Incrementer/Decrementer

The incrementer/decrementer is a 24-bit register. After every 1-unit transfer, that increments (adds) or

decrements (subtract) the contents of SARi and DARi.

Table 13.2.6 lists the increment/decrement values.

Table 13.2.6 Increment/Decrement values

Transfer unit

8 bits

16 bits

Address directions

Forward

Backward

+ 1

– 1

+ 2

– 2

13.2.8 Decrementer

The decrementer is a 24-bit register. After every 1-unit transfer, that decrements the contents of TCRi by

1 when the transfer unit is 8 bits, and by 2 when 16 bits.

In the array chain transfer mode, every time a transfer parameter is read, the contents of the TCRi latch

are also decremented by 1.

13.2.9 DMA latch

The DMA latch is a 16-bit latch.

In 2-bus cycle transfer mode, the DMA latch maintains the value read from the transfer source memory with

a read cycle until this value is written into the transfer destination memory.

In 1-bus cycle transfer mode, the DMA latch is used to copy data. For copy, refer to section “13.4.2 1-bus

cycle transfer.”

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