7721 datasheet(293/577 Pages) RENESAS

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7721 Group User’s Manual

13-14

DMA CONTROLLER

13.2 Block description

13.2.10 DMAi mode register L

Figure 13.2.6 shows the structure of DMAi mode register L. For bit 0, refer to section “13.1.3 (2) Transfer

unit.” For bit 1, refer to section “13.4.1 2-bus cycle transfer” and section “13.4.2 1-bus cycle transfer”;

for bit 2, refer to section “13.4.3 Burst transfer mode” and section “13.4.4 Cycle-steal transfer mode.”

(1)

Transfer source address direction select bits (bits 4 and 5) and Transfer destination address

direction select bits (bits 6 and 7)

Address direction means an order of accessing memory in DMA transfer and is defined as follows:

• Fixed direction: an address does not move.

• Forward direction: an address moves upward from the specified start address.

• Backward direction: an address moves downward from the specified start address.

For details, refer to section “13.4.1 (3) Address directions in 2-bus cycle transfer” and section

“13.4.2 (3) Address directions in 1-bus cycle transfer.”

Fig. 13.2.6 Structure of DMAi mode register L

Bit

Bit name

At reset

Functions

DMA0 mode register L (Address 1FCC16)

DMA1 mode register L (Address 1FDC16)

DMA2 mode register L (Address 1FEC16)

DMA3 mode register L (Address 1FFC16)

Note: When the external data bus has a width of 8 bits and 1-bus cycle transfer is selected, set

bit 0 to “1.”

0 : 16 bits

1 : 8 bits

0 : 2-bus cycle transfer

1 : 1-bus cycle transfer

0 : Burst transfer mode

1 : Cycle-steal transfer mode

0 0 : Fixed

0 1 : Forward

1 0 : Backward

1 1 : Do not select.

Number-of-unit-transfer-bits

select bit (Note)

Transfer method select bit

Transfer mode select bit

Fix this bit to “0.”

Transfer source address

direction select bits

Transfer destination address

direction select bits

0 0 : Fixed

0 1 : Forward

1 0 : Backward

1 1 : Do not select.

b5b4

b7b6

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