7906 datasheet(359/531 Pages) RENESAS

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POWER SAVING FUNCTIONS

7906 Group User’s Manual Rev.2.0

16-6

16.2 Inactivity of system clock in wait mode

In the wait mode, if there is not need to operate the internal peripheral devices, setting the system clock

stop select bit at WIT (See Figure 16.1.3.) to “1” makes the following clocks inactive: the operating clocks

for the internal peripheral devices and fsys. This saves the power consumption of the microcomputer.

Table 16.2.1 lists the states and operations in the wait mode and after this mode is terminated.

Table 16.2.1 States and operations in wait mode and after this mode is terminated

Active.

Operates (Note).

Inactive.

Active.

Inactive.

Operates.

Stopped.

Retains the state at the WIT instruction execution.

System clock is inactive. (bit 3 at address 6316 = 1)

Inactive.

Can operate only in the event counter mode.

Can operate only when an external clock is selected.

Stopped.

Item

Termination due to

interrupt request

occurrence

Timers A, B

Serial I/O

A-D converter

D-A converter

Watchdog timer

Pins

Oscillation

PLL frequency multiplier

φCPU, φBIU

fsys, Clock

φ1,

f1 to f4096

Wf32, Wf512

System clock is active. (bit 3 at address 6316 = 0)

Note: This applies when the PLL circuit operation enable bit (bit 1 at address BC16) = “1.”

Termination due to

hardware reset

Supply of

φCPU, φBIU starts immediately just after termination.

Operation after hardware reset

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