7906 datasheet(387/531 Pages) RENESAS

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FLASH MEMORY VERSION

7906 Group User’s Manual Rev.2.0

19-10

19.2 Flash memory CPU reprogramming mode

19.2.1 Flash memory control register

Figure 19.2.1 shows the structure of the flash memory control register.

(1) RY/BY status bit (bit 0)

This bit is used to indicate the operating status of the sequencer. This bit is “0” during the automatic

programming or erase operation is active and becomes “1” upon completion of them. This bit also

changes during the execution of the programming, block erase, or erase all blocks command, but does

not change owing to the execution of another command.

(2) CPU reprogramming mode select bit (bit 1)

Setting this bit to “1” allows the microcomputer to enter the flash memory CPU reprogramming mode

to accept commands. In order to set this bit to “1,” write “1” followed with “0” successively; while to

clear this bit to “0,” write “0.”

Since the microcomputer enters the flash memory CPU reprogramming mode after setting this bit to

“1,” opcodes cannot be fetched for the internal flash memory. Accordingly, be sure to execute the

instruction to be used for writing to this bit in an area other than the internal flash memory area (e.g.

the internal RAM area).

When executing commands of the flash memory CPU reprogramming mode in the boot mode, be sure

to set the user ROM area select bit (bit 5) to “1.”

Fig. 19.2.1 Structure of flash memory control register

7, 6

RY/BY status bit

CPU reprogramming mode select bit

The value is “0” at reading.

Flash memory reset bit (Note 3)

The value is “0” at reading.

User ROM area select bit

(Valid in boot mode)

(Note 5)

The value is “0” at reading.

(Notes 1, 2)

—

(Note 4)

—

(Note 2)

—

Bit name

Bit

Flash memory control register (Address 9E16)

Function

At reset

R/W

b7 b6 b5 b4 b3 b2 b1 b0

0 : BUSY (Automatic programming or erase operation

is active.)

1 : READY (Automatic programming or erase operation

has been completed.)

0 : Flash memory CPU reprogramming mode is invalid.

1 : Flash memory CPU reprogramming mode is valid.

Notes 1: In order to set this bit to “1,” write “0” followed with “1” successively; while in order to clear this bit “0,” write “0.”

2: Writing to this bit must be performed in an area other than the internal flash memory.

3: This bit is valid when the CPU reprogramming mode select bit (bit 1) = “1”: on the other hand, when the CPU

reprogramming mode select bit = “0,” be sure to fix this bit to “0.” Rewriting of this bit must be performed with the CPU

reprogramming mode select bit = “1.”

4: After writing of “1” to this bit, be sure to confirm the RY/BY status bit (bit 0) becomes “1”; and then, write “0” to this bit.

5: When MD1 = Vss level, this bit is invalid. (It may be either “0” or “1.”)

0 : Access to boot ROM area

1 : Access to user ROM area

Writing “1” into this bit discontinues the access to the

internal flash memory. This causes the built-in flash

memory circuit being reset.

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