7906 datasheet(107/531 Pages) RENESAS

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TIMER A

7906 Group User’s Manual Rev.2.0

7-4

7.2 Block description

Figure 7.2.1 shows the block diagram of timer Aj (j = 0 to 2, 4, 9). Figure 7.2.2 shows the block diagram

of timer Ak (k = 3, 5 to 8). Explanation of registers relevant to timer A is described below.

7.2 Block description

Fig. 7.2.1 Block diagram of timer Aj (j = 0 to 2, 4, 9)

Data bus (odd)

Data bus (even)

f16

f512

Count source

select bit

Timer mode

One-shot pulse mode

PWM mode

Polarity

switching

Timer mode

(Gate function)

Event counter mode

Trigger

Count start bit

Countdown

Up-down bit

(Low-order 8 bits)

(High-order 8 bits)

Timer Aj reload register (16)

Timer Aj counter (16)

Timer Aj

interrupt

request bit

Countup/Countdown

switching

(Always “countdown” except

for in the event counter

mode)

Toggle

F.F.

Pulse output

function select bit

TAjIN

TAjOUT

Note: Common to timers A0 to A9.

f64

f4096

Timer A clock division

select bits (Note)

Fig. 7.2.2 Block diagram of timer Ak (k = 3, 5 to 8)

Data bus (odd)

Data bus (even)

Timer mode

Count start bit

(Low-order 8 bits)

(High-order 8 bits)

Timer Ak reload register (16)

Timer Ak counter (16)

Timer Ak

interrupt

request bit

f4096

Count source

select bit

f16

f512

f64

Timer A clock division

select bits (Note)

Note: Common to timers A0 to A9.

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