TIR2000 datasheet(42/63 Pages) TI

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4–6

4.7

Auxiliary Baud–Rate Divisor Lower Register (ABDL) – (write only)

Address: E (Hex) – Bank 3

Baud-rate divisor lower 8–bit for TV, SIR and SHARP mode

Bit No.

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

4.8

Auxiliary Baud–Rate Divisor Higher Register (ABDH) – (write only)

Address: F (Hex) – Bank 3

Baud-rate divisor higher 8–bit for the TV, SIR and SHARP modes.

Bit No.

Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

4.9

Mode Definition Register (MDR) – (read and write)

Address: 8 (Hex)

MDR

Bit No.

Description

Frame end

mode select

µs Ir pulse

select method

SCT mode

enable

Low power

mode enable

Sleep mode

enable

Mode select

Default

000

Bit definition:

BIT NO.

DESCRIPTIONS

0–2

Mode of operation. Bits 0–2 select the mode of operation as follows:

000

UART

001

SIR

010

SHARP

011

MIR

100

FIR

101

110

Reserved

111

Reserved

Sleep-mode enable. When bit 3 is set to 1, sleep mode is enabled. When set to 1 and other conditions are

satisfied, the device goes into the sleep mode. See paragraph 4.9.1.

Low power mode enable. When bit 4 is set to 1, bit 4 enables the low power mode. When set to 1 and other

conditions are satisfied, the device goes to low-power mode. See paragraph 4.9.2.

Store and controlled transmission enable. When bit 5 is set to 1, store and controlled transmission mode

is enabled.

µs Ir pulse select method. Bit 6 selects the 2-µs Ir pulse select method. Set 1 to select 2-µs Ir pulse.

When set to a 1, bit 7 selects the Set-EOT-bit method. When a 0, bit 7 selects the frame-length method.

See paragraph 2.1.1.1

TIR2000 Datasheet(PDF) 42 Page - Texas Instruments

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