TIR2000 datasheet(32/63 Pages) TI

32 / 63 page

3–2

3.4

Interrupt Identification Register (IIR) - (read only)

Address: 2 (Hex)

Bit Definitions:

BIT NO.

DEFAULT

DESCRIPTION

Interrupt pending

Interrupt ID0

Interrupt ID1

Interrupt ID2

Reserved (always 0)

FIFO enabled 1

FIFO enabled 2

FIFO enabled 3

(bit 7 bit 6 bit 5) = 000

= 110

= 111

FIFO disabled

16-byte FIFO

64-byte FIFO

INTERRUPT ID REGISTER

PRIORITY

INTERRUPT

INTERRUPT SOURCE

INTERRUPT RESET

BIT 3

BIT 2

BIT 1

BIT 0

LEVEL

TYPE

METHOD

None

Receiver line

status

Overrun error, parity error,

framing

error

break

interrupt

Read the line-status

Received data

available

Receiver data available or

trigger level reached in the

FIFO mode

Read

the

receiver

buffer register

Character

time-out

indication

No characters have been

removed from or input to the

receiver FIFO during the last

4 character times, and there

is at least 1 character in it

during this time.

Read

the

receiver

buffer register

Transmitter

holding-register

empty

Transmitter holding register

is empty

Read

the

interrupt

identification register

write

the

transmitter

holding

Modem status

Clear

send,

data-set

ready,

ring

indicator,

data-carrier detect

Read the

modem-status

TIR2000 Datasheet(PDF) 32 Page - Texas Instruments

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