TIR2000 datasheet(50/63 Pages) TI

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4–14

4.13.3

DMA CHANNEL SELECT REGISTER (DCSR) – (write only)

Address: C (Hex) – Bank 2

Bit No.

Definition

Status FIFO reset

Enable DRQ

RX DMA channel select

TX DMA channel select

Default

000

Bits [2–0]: TX DMA channel select. Set these bits as shown to select the data transmission DMA channel

for interrupt and acknowledge.

DCSR[2–0]

DMA channel

001

DRQ0/DACK0

010

DRQ1/DACK1

100

DRQ3/DACK3

Bits [5–3]: RX DMA channel select. Set these bits as shown to select the data receive DMA channel for

interrupt and acknowledge.

DCSR[5–3]

DMA channel

001

DRQ0/DACK0

010

DRQ1/DACK1

100

DRQ3/DACK3

NOTE:

The same channel cannot be selected for both data transmission and data receive

at the same time. If selected, the DMA channel output will be disabled (driven to

a high impedance state). For the UART application, where both data transmission

and data receive interrupts are active simultaneously, separate channels have to

be assigned for data transmit and data receive. However for the infrared mode of

operation, where data transmit and data receive are not active at the same time,

a particular channel can be selected alternately for data transmit and data receive.

Bit 6: When bit 6 is set to a 1, it enables the selected DRQ channel.

Bit 7: Status FIFO is reset by writing a 1 to this bit. Bit 7 is self clearing.

4.14 Bank 3 Registers

4.14.1

General Purpose I/O Direction Register (GPIODIR) – (write only)

Address: B (Hex) – Bank 3

Bit no.

Definition

The corresponding bit is the direction bit for that GPIO terminal. When a 0, the GPIO terminal is an output

and when a 1, the GPIO terminal is an input.

Default

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