TIR2000 datasheet(15/63 Pages) TI

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2–3

Reset the TX FIFO. This includes:

•

Write to the LCR register so that the LCR[7] bit is a 1. The LCR[7] bit must be a 1 to be able to

write to the FCR[5] bit.

•

Program the FCR register to select 64-/16-bytes of the TX FIFO, the non-DMA/DMA mode of

operation, select the TX FIFO trigger level and to clear the TX FIFO.

•

Write the LCR register to set the LCR[7] bit to a 0 for normal operation.

Program the IER register to enable only the transmitter related interrupts and disable the

remaining interrupts. Enable the following:

For programmed I/O mode

•

Transmitter FIFO below threshold level interrupt enable (IER[1])

•

Transmitter underrun interrupt enable (IER[7])

For DMA mode

•

Status FIFO time-out interrupt enable (IER[2])

•

Status FIFO threshold interrupt enable (IER[4])

•

Transmitter underrun interrupt enable (IER[6])

Write a 1 to the ACREG[7] bit to enable data transmission

Write a 1 to the MCR[3] bit. This enables the selected IRQ channel.

2.1.1.1.1

Frame-Closing Methods

There are two ways a transmission frame can be properly terminated: frame-length method and set-EOT

bit method. The two methods are described as follows:

•

Frame-Length method: This method is selected when the MDR[7] bit equals 0. The CPU writes

the frame-length value to the TXFLH and TXFLL registers. The device automatically attaches an

end flag to the frame when the number of bytes transmitted becomes equal to the TXFLH and

TXFLL value.

•

Set-EOT bit method: This method is selected when the MDR[7] bit equals 1. The CPU writes a

1 to the EOT bit of the ACREG[0] register just before it writes the last byte to the TX FIFO. When

the CPU writes the last byte to the TX FIFO, the device internally sets the tag bit for that particular

byte in the TX FIFO. As the peripheral device in the transmit mode reads bytes from the TX FIFO,

the flag-bit information is used to attach an end flag and properly terminate the frame.

2.1.1.1.2

Store and Controlled Data Transmission

In the store and controlled transmission (SCT), the CPU initially writes (stores) the data in the TX FIFO. After

the CPU writes a part of the frame (for a bigger frame) or the whole frame (a small frame such as a

supervisory frame), it enables another bit (ACREG[2] in this case) to start transmission. The SCT is effective

when the CPU writes a 1 to the MDR[5] bit. This method of transmission is different from the normal mode

of transmission (MDR[5] = 0) where transmission of data starts right after the CPU writes the first byte to

the TX FIFO. The SCT sends short frames without a TX underrun.

TIR2000 Datasheet(PDF) 15 Page - Texas Instruments

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