TIR2000 datasheet(31/63 Pages) TI

31 / 63 page

3–1

3 Register Definitions for the UART, SIR and SHARP Modes

3.1

Receiver-Buffer Register (RBR) – (read only)

The receiver buffer register is used to access the receiver-holding register when the RX FIFO register is

disabled, or the RX FIFO when the RX FIFO is enabled. Address: 0 (hex) – LCR[7] bit should be a 0.

3.2

Transmitter Holding Register (THR) – (write only)

The transmitter holding register is used to access the transmitter (TX) holding register when the TX FIFO

is disabled, or the TX FIFO when the TX FIFO is enabled. Address: 0 (hex) – LCR[7] bit should be a 0.

3.3

Interrupt Enable Register (IER) – (read and write)

Address: 1 (hex) – LCR[7] bit should be a 0.

Bit definitions are as follows:

BIT NO.

DEFAULT

DESCRIPTIONS

Receiveddata-available interrupt enable (1 = enable, 0 = disable). When set, bit 0 enables

an interrupt when the receiver FIFO is equal to or above its threshold level.

Transmitter holding-register-empty interrupt enable.

Receiver line-status interrupt enable.

Modem-status interrupt enable.

Not used

Transmitter underrun interrupt enable

TIR2000 Datasheet(PDF) 31 Page - Texas Instruments