TIR2000 datasheet(24/63 Pages) TI

24 / 63 page

2–12

•

Enable/disable the sleep mode. For normal operation, the sleep mode is disabled.

•

Enable/disable the store and controlled data transmission. For normal operation, disable the

SCT.

•

Select the frame-closing method to set-EOT-bit (MDR[7]) to 1.

Program the TV configuration register (TVCFG) to:

•

Select the modulation mode (C_PLS, 6_PLS OR 8_PLS).

•

Enable/disable the receiver internal demodulation.

•

Select programmed T-period mode or over-sampling mode. For normal operation select

programmed T-period mode.

•

Enable/disable the run-length coding mode.

•

Select the TX carrier-frequency range.

•

Select the RX carrier-frequency range.

•

Write a 0 to the RX-active bit (TVCFG[7]). When set to a 1, this bit sets the device to sample

the infrared data even if the carrier frequency is out of range. This bit is normally used to

disable the RX when required. The RX automatically enables when infrared is detected and

the carrier frequency is in the programmed range.

2.1.5.1

TV Data-Transmission Mode

The following register programming steps are required for data transmission in the TV mode:

Program the PLR to select the TX FIFO trigger level

Reset the TX FIFO. This includes the following:

•

Write to the LCR register to set the LCR[7] bit to a 1. The LCR[7] bit must be a 1 to be able to

write to the FCR(5) bit.

•

Program the FCR register to select 64-/16-bytes TX FIFO, non-DMA mode of operation,

select the RX FIFO trigger level and to clear the TX FIFO.

•

Write the LCR register so that the LCR[7] bit = 0 (for normal operation).

Program the IER register to enable only the data-transmission related interrupts. This includes

the following:

•

Enable the TX threshold interrupt.

•

Enable the TX underrun interrupt.

•

Disable the RX FIFO over threshold interrupt.

•

Disable the RX FIFO overrun error interrupt.

Program the TX modulation carrier-frequency register (TVMDCFG) to select the desired carrier

frequency and its pulse duration.

Write a 1 to the ACREG[7] bit to enable data transmission.

Write a 1 to the MCR[3] bit to enable the selected IRQ channel.

This completes the programming of registers and the device is ready for data transmission. The TV data

transmission only supports the set-EOT-bit method, thus the CPU must write a 1 to the ACREG[0] bit prior

to writing the last byte of a frame to the TX FIFO. The CPU receives an interrupt and reads the IIR to identify

TIR2000 Datasheet(PDF) 24 Page - Texas Instruments

TIR2000 Datasheet(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL