TIR2000 datasheet(37/63 Pages) TI

37 / 63 page

4–1

4 Register Definitions for the MIR, FIR and TV Modes

4.1

Receiver Buffer Register (RBR) – (read only)

Address: 0 (Hex)

LCR[7] bit must be a 0 to read this register. This register is used to read data from the RX FIFO register.

4.2

Transmitter Holding Register (THR) – (write only)

Address: 0 (Hex)

LCR[7] bit must be a 0 to read this register. This register is used to read data from the TX FIFO register.

4.3

Interrupt Enable Register (IER) – (read and write)

Address: 1 (Hex) - LCR[7] bit must be a 0 to access this register.

MIR/FIR (Programmed I/O) Mode

Bit definition:

BIT NO.

DEFAULT

DESCRIPTIONS

Received–data–available interrupt enable (1 = enable, 0 = disable).

If bit 0 is a 1, it enables an interrupt when the receiver FIFO is equal to or above the set

threshold level.

Transmitter FIFO below threshold level interrupt enable. If bit 1 is a 1, it enables an interrupt

when the transmitter FIFO is below the set threshold level.

Last byte from RX FIFO enable. (1 = enable, 0 = disable)

If bit 2 is a 1, it enables an interrupt when the CPU reads the last byte of a frame from the

RX FIFO.

RX FIFO overrun interrupt enable.

Write 0

Transmitter underrun interrupt enable.

Write 0

Received end–of–frame interrupt enable.

MIR/FIR (DMA) Mode

Bit definition:

BIT NO.

DEFAULT

DESCRIPTIONS

Write 0

Status FIFO time-out interrupt enable. When set to a 1, an interrupt is generated when the

interframe gap between successive frames is 1 ms.

Write 0

Status FIFO threshold interrupt enable. When set to a 1, bit 4 enables the Status FIFO

threshold interrupt, i.e. When the Status FIFO level is equal to or above its threshold level,

an interrupt is generated.

Transmitter underrun interrupt enable.

DMA terminal count interrupt enable.

Write 0

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