TIR2000 datasheet(46/63 Pages) TI

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4–10

4.11.7

Status FIFO Line Status Register (SFLSR) – (read only)

Address A (Hex) – Bank 0

Bit No.

[7–5]

Definition

Not used

Status FIFO empty

Overrun errors

Frame length error

PHY error

CRC error

Default

Bit definition:

BIT NO.

DESCRIPTIONS

CRC Error . Bit 0 is set to a 1 when a bad CRC is detected on data receive for that particular frame.

PHY error. In the FIR mode, bit 1 is set to a 1 when an illegal symbol is received during data reception for

that particular frame. In the MIR mode, bit 1 is set to a 1 when an abort pattern (at least 7 consecutive 1’s)

is received during data reception.

Frame-too-long. Bit 2 is set to a 1 when a frame exceeding the maximum length (set by the RXFLH and

RXFLL registers) has been received.

Overrun error. Bit 3 is set to a 1 when an overrun in the RXFIFO occurs.

Bit 4 is set to a 1 when the Status FIFO is empty. The CPU uses bit 4, not the LSR[1] bit, to determine the

empty status when it receives a Status FIFO threshold interrupt.

4.11.8

Status FIFO Register Low (SFREGL) – (read only)

Address C (Hex), – Bank 0

4.11.9

Status FIFO Register High (SFREGH) – (read only)

Address D (Hex) – Bank 0

The length of each frame is stored in the Status FIFO register. When the CPU executes a read transaction

with address C (Bank 0), status FIFO[7–0] bits are loaded to the bus. When the CPU executes a read

transaction with address D (Bank 0), status FIFO[11–8] bits are loaded to the bus.

4.11.10 Resume Register (RESUME) (read only)

Address B (Hex) – Bank 0

When transmit underrun or receive overrun occurs this register should be read to resume normal operation.

4.12 Bank 1 Registers

4.12.1

TV Configuration Register (TVCFG)

Address: A (Hex) – Bank 1

Bit No.

[1:0]

Description

active

Run

length

coding

enable

0 = programmed

T mode

1 = over-

sampling mode

RX carrier

frequency

range

0 = 30K–56K

1 = 400K–500K

RCVR

internal

demodulation

disable

TX carrier

frequency range

0 = 30K–56K Hz

1 = 400K–500K Hz

Modulation

mode

00 = C_PLS

01 = 8_PLS

10 = 6_PLS

11 = Reserved

Default

TIR2000 Datasheet(PDF) 46 Page - Texas Instruments

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