TIR2000 datasheet(25/63 Pages) TI

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2–13

the source of the interrupt. If the source of the interrupt is IIR[1] (TX FIFO below the threshold interrupt), the

CPU must:

•

Disable the IER[1] bit

•

Write data bytes to the TX FIFO. The maximum number of data bytes is limited to the number

selected by the TX FIFO trigger level.

•

Enable the IER[1] bit

If the source of the interrupt is a IIR[5] bit, an underrun has occurred while transmitting and the CPU must

service the underrun. See paragraph 2.1.1.1.4.

2.1.5.2

TV Receive Mode

The following register programming steps are required for data receive in the TV mode:

Program the infrared configuration register (IRCFG). Select the TV infrared receive terminal to

be either IRRVL (IRCFG[1] = 1) or IRRVH (IRCFG[1] = 0).

Program the RX demodulation configuration register (TVDMCFG). Select the desired incoming

infrared data carrier frequency range.

Reset the RX FIFO. This includes the following:

•

Write to the LCR register to set the LCR[7] bit to a 1. The LCR[7] bit must be a 1 in order to be

able to write to the FCR(5) bit.

•

Program the FCR to select 64-/16-bytes TX FIFO, non-DMA mode of operation, select the

RX FIFO trigger level and to clear the TX FIFO.

•

Write the LCR register so that bit LCR[7] = 0 (for normal operation).

Program the IER register to enable only the receive related interrupts which include:

•

RX threshold interrupt (IER[0].

•

RX FIFO overrun (IER[3]).

•

Disable the TX related interrupts (TX FIFO below threshold interrupt and the TX underrun

interrupt).

Write a 1 to the ACREG[6] bit to enable data receive.

Write a 1 to the MCR[3] bit to enable the selected IRQ channel.

This completes the programming of the registers for data receive and now the device is ready to receive

data. The CPU receives an interrupt and reads the IIR to identify the source of the interrupt. If the source

of the interrupt is IIR[0], the CPU goes to the threshold mode. See paragraph 2.1.1.2.1. If the source of the

interrupt is IIR[4], an overrun has occurred while receiving data and the CPU needs to service the overrun.

See paragraph 2.1.1.2.3.

To stop data receive after the End-Of-Frame flag (EOF) is detected by the CPU, write a 0 to the

TVCFG[7] bit.

2.1.6

Universal Asynchronous Receiver Transmitter (UART) mode

The UART mode is the default mode of operation after power up and system reset. This mode uses a wired

interface for serial communication with a remote device or a modem. The TIR2000 can operate in a

full-duplex mode, i.e. data transmission and reception can take place simultaneously.

The TIR2000 in the UART mode works as a regular serial asynchronous communication controller that

converts the parallel data received from the CPU or the DMA controller to serial data. It also converts the

serial data received on the serial input terminal to parallel data.

TIR2000 Datasheet(PDF) 25 Page - Texas Instruments

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