XRT86VL30 datasheet(27/188 Pages) EXAR

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XRT86VL30

REV. 1.0.0

SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

CRC-4 Bits Source Sel

R/W

CRC-4 Bits Source Select

This bit permits the user to specify the source of the CRC-4 bits,

within the outbound E1 data-stream, as depicted below.

0 - Configures the Transmit E1 Framer block to internally compute

and insert the CRC-4 bits within the outbound E1 data-stream.

1 - Configures the Transmit E1 Framer block to externally accept

data from the TxSer_n input pin, and to insert this data into the CRC-

4 bits within the outbound E1 data-stream.

NOTE: This bit is ignored if CRC Multiframe Alignment is disabled

Framing Alignment Pat-

tern Source Select

R/W

Framing Alignment Pattern Source Select

This bit permits the user to specify the source of the various “Fram-

ing Alignment” bits (which includes the FAS bits, the CRC Multiframe

Alignment bits, the E and A bits).

0 - Configures the Transmit E1 Framer block to internally generate

and insert these various framing alignment bits into the outbound E1

data-stream.

1 - Configures the Transmit E1 Framer block to externally accept

data from the TxSer_n input pin, and to insert this data into the FAS,

CRC Multiframe, E and A bits within the outbound E1 data-stream.

NOTE: Users can specify the source for E-bits in register bits 6-7

within this register if Transmit E1 Framer is configured to

internally generate the various framing alignment bits (i.e.

this bit set to’0’).

TABLE 6: SYNCHRONIZATION MUX REGISTER (SMR)

HEX ADDRESS: 0X0109

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

XRT86VL30 Datasheet(PDF) 27 Page - Exar Corporation