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XRT86VL30 Datasheet(PDF) 69 Page - Exar Corporation |
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XRT86VL30 Datasheet(HTML) 69 Page - Exar Corporation |
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69 / 188 page ![]() XRT86VL30 64 REV. 1.0.0 SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION The following table demonstrates the conditions on receive side which trigger the Automatic Sa, E, and A bits transmission when TSACR2 bits are enabled. TABLE 44: CONDITIONS ON RECEIVE SIDE WHEN TSACR2 BITS ENABLED CONDITIONS ACTIONS - SENDING PATTERN FOR A SA5 SA6 E AIS_1_ENB 1 1 1111 X AIS_2_ENB 0 1 1111 x CRCREP_ENB = 01, CRC reported (E = 0) 0 1 0000 0 CRCREP_ENB = 10, CRC reported 0 0 0000 0 CRCREP_ENB = 11, CRC reported 0 1 0001 1 CRCDET_ENB 0 1 0010 1 CRCDET/REP_ENB 0 1 0011 1 |
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