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XRT86VL30 Datasheet(PDF) 68 Page - Exar Corporation |
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XRT86VL30 Datasheet(HTML) 68 Page - Exar Corporation |
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68 / 188 page  XRT86VL30 63 SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION REV. 1.0.0 TABLE 43: TRANSMIT Sa AUTO CONTROL REGISTER 2 (TSACR2) HEX ADDRESS: 0X0132 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 AIS_1_ENB R/W 0 AIS reception This bit enables the automatic Sa-bit transmission upon detecting AIS condition. Upon detecting the AIS condition, E1 framer will transmit the Alarm bit (A bit) as ‘1’, Sa5 bit as ‘1’, and Sa6 bit as ‘1’. See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon detecting AIS condition. 6 AIS_2_ENB R/W 0 AIS reception This bit enables the automatic Sa-bit transmission upon detecting AIS condition. Upon detecting the AIS condition, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, and Sa6 bit as ‘1’. See Table 44 for the transmit Sa5, Sa6, and A bit pattern upon detecting AIS condition. 5 Reserved - - Reserved 4 Reserved - - Reserved 3 CRCREP_ENB[1] R/W 0 CRC report These two bits enable the automatic Sa-bit transmission upon detecting Far End Block Error (i.e. received E bit = 0). Upon detecting the Far End Block Error (FEBE) condition, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0000’, and E bit as ‘0’ pattern if these two bits are set to ‘01’. If these two bits are set to ‘10’, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘0’, Sa6 bit as ‘0000’, and E bit as ‘0’ pattern upon detecting the Far End Block Error (FEBE). If these two bits are set to ‘11’, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0001’, and E bit as ‘1’ pattern upon detecting the Far End Block Error (FEBE). See Table 44 for the transmit Sa5, Sa6, E, and A bit pattern upon detecting FEBE condition. 2 CRCREP_ENB[0] R/W 0 1 CRCDET_ENB R/W 0 CRC detection This bit enables the automatic Sa-bit transmission upon detecting CRC-4 error condition. Upon detecting CRC-4 error condition, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0010’, and E bit as ‘1’ pattern. See Table 44 for the transmit Sa5, Sa6, E, and A bit pattern upon detecting CRC-4 error condition. 0 CRCREC AND DET_ENB R/W 0 CRC report and detect This bit enables automatic Sa-bit transmission upon detecting both Far End Block Error (FEBE) and CRC-4 error conditions. Upon detecting both Far End Block Error (FEBE) and CRC-4 error condition, E1 framer will transmit the Alarm bit (A bit) as ‘0’, Sa5 bit as ‘1’, Sa6 bit as ‘0011’, and E bit as ‘1’ pattern. See Table 44 for the transmit Sa5, Sa6, E, and A bit pattern upon detecting both FEBE and CRC-4 error conditions. |
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