XRT86VL30 datasheet(48/188 Pages) EXAR

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XRT86VL30

SINGLE T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

REV. 1.0.0

TABLE 23: INTERRUPT CONTROL REGISTER (ICR)

HEX ADDRESS: 0X011A

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

7-3

Reserved

INT_WC_RUR

R/W

Interrupt Write-to-Clear or Reset-upon-Read Select

This bit configures all Interrupt Status bits to be either Reset Upon

Read or Write-to-Clear

0 = Configures all Interrupt Status bits to be Reset Upon Read

(RUR).

1= Configures all Interrupt Status bits to be Write-to-Clear (WC).

ENBCLR

R/W

Interrupt Enable Auto Clear

This bit configures all interrupt enable bits to clear or not clear after

reading the interrupt status bit.

0= Configures all Interrupt Enable bits to not cleared after reading

the interrupt status bit. The corresponding Interrupt Enable bit will

stay ‘high’ after reading the interrupt status bit.

1= Configures all interrupt Enable bits to clear after reading the

interrupt status bit. The corresponding interrupt enable bit will be set

to ‘low’ after reading the interrupt status bit.

INTRUP_ENB

R/W

Interrupt Enable for Framer_n

This bit enables the entire E1 Framer Block for Interrupt Generation.

0 = Disables the E1 framer block for Interrupt Generation

1 = Enables the E1 framer block for Interrupt Generation

XRT86VL30 Datasheet(PDF) 48 Page - Exar Corporation