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AD9122

Rev. 0 | Page 52 of 56

This completes the synchronization procedure, and at this stage,

all devices should be synchronized.

To ensure that each of the DACs are updated with the correct

data on the same CLK edge, two timing relationships must be

met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must

meet the setup-and-hold times with respect to the rising edge of

DACCLK, and REFCLK must also meet the setup-and-hold time

with respect to the rising edge of DACCLK. When resetting the

FIFO, the FRAME signal must be held high the time required to

input two complete data input words. When these conditions are

met, the outputs of the DACs are updated within tSKEW + tOUTDLY

nanoseconds of each other. A timing diagram that illustrates the

timing requirements of the input signals is shown in Figure 82.

DACCLKP(1)/

DACCLKN(1)

DACCLKP(2)/

DACCLKN(2)

REFCLKP(2)/

REFCLKN(2)

DCIP(2)/

DCIN(2)

FRAMEP(2)/

FRAMEN(3)

tSKEW

tSU_SYNC

tSU_DCI tH_DCI

tH_SYNC

Figure 82. Data Rate Synchronization Signal Timing Requirements,

2x Interpolation

Figure 82 shows the synchronization signal timing with 2×

interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is

shown to be equal to the data rate. The maximum frequency at

which the device can be resynchronized in data rate mode can

be expressed as

fSYNC_I = fDATA/2N

where N is any nonnegative integer.

Generally, for values of N equal to or greater than 3, select the

FIFO rate synchronization mode.

FIFO RATE MODE SYNCHRONIZATION

The Procedure for FIFO Rate Synchronization when Directly

Sourcing the DAC Sampling Clock section outlines the steps

required to synchronize multiple devices in FIFO rate mode.

The procedure assumes that the REFCLK and DACCLK signals

are applied to all of the devices. The procedure must be carried

out on each individual device.

Procedure for FIFO Rate Synchronization when Directly

Sourcing the DAC Sampling Clock

Configure for FIFO rate, periodic synchronization by writing

0x80 to the sync control register (Register 0x10). Additional

synchronization options are available and are described in the

Additional Synchronization Features section.

Poll the sync locked bit (Register 0x12, Bit[6]) to verify that the

device is back-end synchronized. A high level on this bit indicates

that the clocks are running with a constant and known phase

relative to the sync signal.

Reset the FIFO by strobing the FRAME signal high for the time

required to input to complete input words. Resetting the FIFO

ensures that the correct data is being read from the FIFO of

each of the devices simultaneously.

This completes the synchronization procedure, and at this stage,

all devices should be synchronized.

To ensure that each of the DACs are updated with the correct

data on the same CLK edge, two timing relationships must be

met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must

meet the setup-and-hold times with respect to the rising edge of

DACCLK, and REFCLK must also meet the setup-and-hold

time with respect to the rising edge of DACCLK. When resetting

the FIFO, the FRAME signal must be held high for at least three

data periods (that is, 1.5 cycles of DCI). When these conditions

are met, the outputs of the DACs are updated within tSKEW + tOUTDLY

nanoseconds of each other. A timing diagram that illustrates the

timing requirements of the input signals is shown in Figure 83.

DACCLKP(1)/

DACCLKN(1)

DACCLKP(2)/

DACCLKN(2)

REFCLKP(2)/

REFCLKN(2)

DCIP(2)/

DCIN(2)

FRAMEP(2)/

FRAMEN(2)

tSKEW

tSU_SYNC tH_SYNC

Figure 83. FIFO Rate Synchronization Signal Timing Requirements,

2× Interpolation

Figure 83 shows the synchronization signal timing with 2×

interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is

shown to be equal to the FIFO rate. More generally, the maximum

frequency at which the device can be resynchronized in FIFO

rate mode can be expressed as

fSYNC_I = (fDATA/8 × 2N)

where N is any nonnegative integer.

ADDITIONAL SYNCHRONIZATION FEATURES

The synchronization logic incorporates additional features that

provide means for querying the status of the synchronization,

improving the robustness of the synchronization, and a one shot

synchronization mode. These features are detailed in the Sync

Status Bits and Timing Optimization sections that follow.

AD9122 Datasheet(PDF) 52 Page - Analog Devices

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