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AD9122

Rev. 0 | Page 18 of 56

SERIAL PORT OPTIONS

The serial port can support both MSB-first and LSB-first data

formats. This functionality is controlled by LSB_FIRST

(Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0).

When LSB_FIRST = 0 (MSB-first), the instruction and data bit

must be written from MSB to LSB. Multibyte data transfers in

MSB-first format start with an instruction byte that includes

the register address of the most significant data byte. Subsequent

data bytes should follow from the high address to low address.

In MSB-first mode, the serial port internal byte address

generator decrements for each data byte of the multibyte

communication cycle.

When LSB_FIRST = 1 (LSB-first), the instruction and data bit

must be written from LSB to MSB. Multibyte data transfers in

LSB-first format start with an instruction byte that includes the

multiple data bytes. The serial port internal byte address generator

increments for each byte of the multibyte communication cycle.

The serial port controller data address decrements from the

data address written toward 0x00 for multibyte I/O operations

if the MSB-first mode is active. The serial port controller address

increments from the data address written toward 0x7F for

multibyte I/O operations if the LSB-first mode is active.

R/W A6

A4 A3

D7 D6N D5N

D00

D10

D20

D30

D7 D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

SDIO

SDO

Figure 37. Serial Register Interface Timing MSB-First

SCLK

SDIO

SDO

A3 A4

N1 R/W D00 D10 D20

D7N

D6N

D5N

D4N

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

Figure 38. Serial Register Interface Timing LSB-First

SCLK

SDIO

INSTRUCTION BIT 6

INSTRUCTION BIT 7

tDS

tDH

tPWH

tPWL

tSCLK

Figure 39. Timing Diagram for Serial Port Register Write

SCLK

SDIO,

SDO

DATA BIT n – 1

DATA BIT n

tDV

Figure 40. Timing Diagram for Serial Port Register Read

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