AD9122 datasheet(32/56 Pages) AD

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AD9122

Rev. 0 | Page 32 of 56

WRITE POINTER

DACS

READ POINTER

32 BITS

÷ INT

DCI

DACCLK

DATA

PATHS

DATA

ASSEMBLER

INPUT

LATCH

REG 0

REG 1

REG 2

REG 3

REG 4

REG 5

REG 6

REG 7

Figure 44. Block Diagram of FIFO

Valid data is transmitted through the FIFO as long as the

FIFO does not overflow or become empty. Note that an over-

flow or empty condition of the FIFO is the same as the write

pointer and read pointer being equal. When both pointers are

equal, an attempt is made to read and write a single FIFO register

simultaneously. This simultaneous register access leads to

unreliable data transfer through the FIFO and must be avoided.

Nominally, data is written to the FIFO at the same rate that data

is read from the FIFO, which keeps the data level in the FIFO

constant. If data is written to the FIFO faster than data is read,

the data level in the FIFO increases. If the data is written to the

device slower than data is read, the data level in the FIFO decreases.

For optimum timing margin, the FIFO level should be maintained

near half full, which is the same as maintaining a difference of

four between the write pointer and read pointer values.

Resetting the FIFO Data Level

To maximize the timing margin between the DCI input and

the internal DAC data rate clock, the FIFO data level should be

initialized prior to beginning data transmission. The value of

the FIFO data level can be initialized in three ways; by resetting

the device, by strobing the FRAME input, and via a write sequence

to the serial port. The two preferred methods are by using of the

FRAME signal and by issuing a command.

As discussed in the Byte Interface Mode and Nibble Interface

Mode sections, the FRAME input is used as a data select signal

that indicates to which DACs the input data is written. The second

function of the FRAME input is initializing the FIFO data level

value. This is done by asserting the FRAME signal high for at

least the time interval needed to load complete data to the I and

Q DACs. This corresponds to one DCI period in word mode,

two DCI periods in byte mode, and four DCI periods in nibble

mode. When FRAME is asserted in this manner, the write pointer

is set to 4 (by default or to the FIFO start level) the next time

the read pointer becomes 0 (see Figure 45).

FIFO WRITE RESETS

READ

POINTER

FRAME

WRITE

POINTER

Figure 45. Timing of the FRAME Input vs. Write Pointer Value

To initialize the FIFO data level through the serial port, Bit 1 of

write to the register is complete, the FIFO data level is initialized.

This method operates similar to the method previously described.

When the initialization is triggered, the next time the read

pointer becomes 0, the write pointer is set to the value of the FIFO

start level (Register 0x17, Bits[2:0]) variable upon initialization. By

default, this is 4 but can be programmed to a value of 0 to 7.

The recommended procedure for a serial port FIFO data level

initialization is as follows:

•

Request FIFO level reset by setting Register 0x18, Bit 1 to 1.

•

Verify the part acknowledges the request by ensuring

•

Remove the request by setting Register 0x18, Bit 1 to 0.

•

Verify the part drops the acknowledge signal by ensuring

Monitoring the FIFO Status

The FIFO initialization and status can be read from Register 0x18.

This register provides information on the FIFO initialization

method, and whether the initialization was successful. The MSB

of Register 0x18 is a FIFO warning flag that can optionally

trigger a device IRQ. This flag is an indication that the FIFO

is close to emptying (FIFO level is 1) or overflowing (FIFO level

is 7). This is an indication that data may soon be corrupted, and

action should be taken.

The FIFO data level can be read from Register 0x19 at any time.

The serial port reported FIFO data level is denoted as a 7-bit

thermometer code of the write counter state relative to the absolute

read counter being at 0. The optimum FIFO data level of 4 is

therefore reported as a value of 00001111 in the status register.

It should be noted that, depending on the timing relationship

between DCI and the main DACCLK, the FIFO level value can be

off by ±1 count. Therefore, it is important to keep the difference

between the read and write pointers to at least 2.

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