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AD9122 Datasheet(PDF) 3 Page - Analog Devices |
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AD9122 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 56 page  AD9122 Rev. 0 | Page 3 of 56 FUNCTIONAL BLOCK DIAGRAM MULTICHIP SYNCHRONIZATION D15P—D15N D0P—D0N FIFO HB1 HB2 HB3 NCO AND MOD fDATA/2 PRE MOD INTERNAL CLOCK TIMING AND CONTROL LOGIC 16 16 10 16 16 I OFFSET Q OFFSET INV SINC AUX 1.2G DAC 1 16-BIT IOUT1P IOUT1N AUX 1.2G DAC 1 16-BIT IOUT2P IOUT2N REF AND BIAS FSADJ DACCLKP DACCLKN REFCLKP REFCLKN REFIO 10 10 DAC CLK SERIAL INPUT/OUTPUT PORT PROGRAMMING REGISTERS POWER-ON RESET 0 1 CLOCK MULTIPLIER (2× TO 16×) CLK RCVR CLK RCVR PLL CONTROL SYNC DAC CLK_SEL DAC_CLK PLL_LOCK DCI FRAME Figure 2. AD9122 Functional Block Diagram |
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