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AD9122

Rev. 0 | Page 33 of 56

INTERFACE TIMING

The timing diagram for the digital interface port is shown

in Figure 46. The sampling point of the data bus occurs about

350 ps after each edge of the DCI signal and has an uncertainty

of ±300 ps, as illustrated by the sampling interval shown in

Figure 46. The DATA and FRAME signals must be valid

throughout this sampling interval. The DATA and FRAME

signals may change at any time between sampling intervals.

The setup (tS) and hold (tH) times with respect to the edges

are shown in Figure 46. The minimum setup and hold times

are shown in Table 13.

DCI

DATA

tDATA

SAMPLING

INTERVAL

SAMPLING

INTERVAL

Figure 46. Timing Diagram for Input Data Ports

Table 13. Data Port Setup and Hold Times

Parameter

Time (ps)

tS (MIN)

−50

tH (MIN)

650

The data interface timing can be verified by using the sample

error detection (SED) circuitry. See the Interface Timing

Validation section for details.

In data rate mode, a second timing constraint between DCI and

DACCLK must be met in addition to the DCI-to-DATA timing

shown in Table 14. In data rate mode, only one FIFO slot is being

used. The DCI to DACCLK timing restriction is required to

prevent data being written to and read from the FIFO slot at the

same time. The required timing between DCI and DACCLK is

shown in Figure 47.

DCI

DACCLK/

REFCLK

tDATA

tSDCI

tHDCI

SAMPLING

INTERVAL

Figure 47. Timing Diagram for Input Data Port (Data Rate Mode)

Table 14. Data Port Setup and Hold Times

Parameter

Time (ps)

tSDCI (MIN)

−120

tHDCI (MIN)

820

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