AD9122 datasheet(24/56 Pages) AD

24 / 56 page

AD9122

Rev. 0 | Page 24 of 56

Reg

Name

Addr

(Hex)

Bit

Name

Description

Default

PLL

Control

7:6

PLL Loop

Bandwidth[1:0]

Selects the PLL loop filter bandwidth.

00 = narrowest bandwidth.

01 = narrow/medium bandwidth.

10 = medium/wide bandwidth.

11 = widest bandwidth.

4:0

PLL Charge Pump

Current[4:0]

Sets the nominal PLL charge pump current.

001

00000 = lowest current setting.

11111 = highest current setting.

PLL

Control

7:6

N2[1:0]

PLL control clock divider. It determines the ratio of the

DACCLK rate to the PLL controller clock rate.

00 = fDACCLK/fPC_CLK = 2.

01 = fDACCLK/fPC_CLK = 4.

10 = fDACCLK/fPC_CLK = 8.

11 = fDACCLK/fPC_CLK = 16.

fPC_CLK must always be less than 50 MHz.

PLL cross control enable

Enable PLL cross point controller.

3:2

N0[1:0]

PLL VCO divider. It determines the ratio of the VCO

output to the DACCLK frequencies.

00 = fVCO/fDACCLK = 1.

01 = fVCO/fDACCLK = 2.

10 = fVCO/fDACCLK = 4.

11 = fVCO/fDACCLK = 4.

1:0

N1[1:0]

PLL Loop divider. It determines the ratio of the DACCLK to

the REFCLK frequencies.

00 = fDACCLK/fREFCLK = 2.

01 = fDACCLK/fREFCLK = 4.

10 = fDACCLK/fREFCLK = 8.

11 = fDACCLK/fREFCLK = 16.

PLL

Status

PLL lock

The PLL generated clock is tracking the REFCLK input signal.

3:0

VCO Control

Voltage[3:0]

VCO Control Voltage readback. See Table 24.

PLL

Status

5:0

VCO Band

Readback[5:0]

Indicates the VCO band currently selected.

Sync

Control

Sync enable

1 = enables the synchronization logic.

Data/FIFO rate toggle

0 = operates the synchronization at the FIFO reset rate.

1 = operates the synchronization at the data rate.

Rising edge sync

0 = sync is initiated on the falling edge of the sync input.

1 = sync is initiated on the rising edge of the sync input.

2:0

Sync Averaging[2:0]

Sets the number of input samples that are averaged in

determining the sync phase.

000 = 1.

001 = 2.

010 = 4.

011 = 8.

100 = 16.

101 = 32.

110 = 64.

111 = 128.

AD9122 Datasheet(PDF) 24 Page - Analog Devices

AD9122 Datasheet(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL