Electronic Components Datasheet Search
  English  ▼

X  

AD9122 Datasheet(PDF) 19 Page - Analog Devices

Part # AD9122
Description  Dual, 16-Bit, 1200 MSPS, TxDAC짰 Digital-to-Analog Converter
PDF  56 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9122 Datasheet(HTML) 19 Page - Analog Devices

Back Button AD9122 Datasheet HTML 15Page - Analog Devices AD9122 Datasheet HTML 16Page - Analog Devices AD9122 Datasheet HTML 17Page - Analog Devices AD9122 Datasheet HTML 18Page - Analog Devices AD9122 Datasheet HTML 19Page - Analog Devices AD9122 Datasheet HTML 20Page - Analog Devices AD9122 Datasheet HTML 21Page - Analog Devices AD9122 Datasheet HTML 22Page - Analog Devices AD9122 Datasheet HTML 23Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 19 / 56 page
background image
AD9122
Rev. 0 | Page 19 of 56
DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS
Table 10. Device Configuration Register Map
Reg Name
Addr
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Comm
0x00
SDIO
LSB_FIRST
Reset
0x00
Power Control
0x01
Power-
down
DAC I
Power-
down
DAC Q
Power-
down data
receiver
Power-
down
aux ADC
PLL lock
status
0x10
Data Format
0x03
Binary
data
format
Q data
first
MSB swap
Data bus width[1:0]
0x00
Interrupt Enable
0x04
Enable
PLL lock
lost
Enable
PLL
locked
Enable
sync
signal
lost
Enable
sync
signal
locked
Enable
sync
phase
locked
Enable
soft
FIFO
sync
Enable
FIFO
Warning 1
Enable
FIFO
Warning 2
0x00
Interrupt Enable
0x05
0
0
0
Enable
AED
compar
pass
Enable
AED
compar
fail
Enable
SED
compar
fail
0
0
0x00
Event Flag
0x06
PLL
lock
lost
PLL
locked
Sync
signal
lost
Sync
signal
locked
Sync
phase
locked
Soft
FIFO
sync
FIFO
Warning 1
FIFO
Warning 2
N/A
Event Flag
0x07
AED
compar
pass
AED
compar
fail
SED
compar
fail
N/A
Clock Receiver
Control
0x08
DACCLK
duty
correction
REFCLK
duty
correction
DACCLK
cross-
correction
REFCLK
cross-
correction
0
0
0
0
0x3F
PLL Control
0x0A
PLL
enable
PLL
manual
enable
Manual VCO Band[5:0]
0x40
PLL Control
0x0B
PLL VCO
enable
0x00
PLL Control
0x0C
PLL Loop
Bandwidth[1:0]
PLL Charge Pump Current[4:0]
0xD1
PLL Control
0x0D
N2[1:0]
PLL cross
control
enable
N0[1:0]
N1[1:0]
0xD9
PLL Status
0x0E
PLL lock
VCO Control Voltage[3:0]
0x00
PLL Status
0x0F
VCO Band Readback[5:0]
0x00
Sync Control
0x10
Sync
enable
Data/FIFO
rate toggle
Rising
edge sync
Sync Averaging[2:0]
0x48
Sync Control
0x11
Sync Phase Request[5:0]
0x00
Sync Status
0x12
Sync lost
Sync
locked
N/A
Sync Status
0x13
Sync Phase Readback[7:0] (6.2 format)
N/A
Data Receiver
Status
0x15
LVDS
FRAME
level high
LVDS
FRAME
level low
LVDS
DCI level
high
LVDS
DCI
level
low
LVDS
data level
high
LVDS data
level low
N/A
FIFO Control
0x17
FIFO Phase Offset[2:0]
0x04
FIFO Status
0x18
FIFO
Warning 1
FIFO
Warning 2
FIFO
soft
align
ack
FIFO soft
align
request
FIFO reset
aligned
N/A
FIFO Status
0x19
FIFO Level[7:0]
N/A



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com