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AD9122

Rev. 0 | Page 31 of 56

LVDS INPUT DATA PORTS

The AD9122 has one LVDS data port that receives data for both

the I and Q transmit paths. The device can accept data in word,

byte, and nibble formats. In word, byte, and nibble modes, the data

is sent over 16-bit, 8-bit, and 4-bit LVDS data busses, respectively.

The pin assignment of the bus in each mode is shown in Table 12.

Table 12. Data Bit Pair Assignments for Data Input Modes

Mode

MSB, …, LSB

Word

D15, D14, …, D0

Byte1

D14, D12, D10, D8, D7, D5, D3, D1

Nibble1

D10, D8, D7, D5

1 In byte and nibble modes, the unused pins can be left floating.

The data is accompanied by a reference bit (DCI) that is used to

generate a double data rate (DDR) clock. In byte and nibble modes,

a FRAME signal is required for controlling to which DAC the

data is sent. All of the interface signals are time aligned. While

there is a maximum skew requirement on the bus, there are no

setup and hold times to be met.

WORD INTERFACE MODE

In word mode, the DCI signal is a reference bit used for

generating the data sampling clock. Time align the DCI

signal with the data. The I DAC data should correspond

with DCI being high and the Q DAC data with DCI being

low, as illustrated in Figure 41.

DCI

DATA[15:0]

Figure 41. Timing Diagram for Word Mode

BYTE INTERFACE MODE

In byte mode, the DCI signal is a reference bit used for generating

the data sampling clock and should be time aligned with the

data. The most significant byte of the data should correspond

with DCI being high, and the least significant byte of the data

should correspond with DCI being low. The FRAME signal

indicates to which DAC the data is sent. When FRAME is high,

data is sent to the I DAC, and when FRAME is low, data is sent

DCI

diagram is shown in Figure 42.

cture. The complete timing

ure 43.

hich significantly increases the

ate, that is, the DACCLK rate divided by the

interpolation ratio.

to the Q DAC. The complete timing

NIBBLE INTERFACE MODE

In nibble mode, the DCI signal is a reference bit used for

generating the data sampling clock and should be time aligned

with the data. The FRAME signal indicates to which DAC the

data is sent. When FRAME is high, data is sent to the I DAC.

When FRAME is low, data is sent to the Q DAC. All four nibbles

must be written to the device for proper operation. For 12-bit

resolution devices, the data in the fourth nibble acts as a plac

holder for the data framing stru

diagram is shown in Fig

FIFO OPERATION

The AD9122 contains a 2-channel, 16-bit wide, eight-word deep

FIFO designed to relax the timing relationship between the data

arriving at the DAC input ports and the internal DAC data rate

clock. The FIFO acts as a buffer that absorbs timing variation

between the data source and DAC, such as the clock-to-data

variation of an FPGA or ASIC, w

timing budget of the interface.

Figure 44 shows the block diagram of the datapath through th

FIFO. The data is latched into the device, is formatted, and is

then written into the FIFO register determined by the FIFO write

pointer. The value of the write pointer is incremented every time a

new word is loaded into the FIFO. Meanwhile, data is read from

the FIFO register determined by the read pointer and fed into

the digital datapath. The value of the read pointer is update

every time data is read into the datapath from the FIFO. This

happens at the data r

DATA[15:0]

FRAME

QLSB

I1MSB

I1LSB

Q1MSB

Q1LSB

I2MSB

I2LSB

Q2MSB

Q2LSB

Figure 42. Timing Diagram for Byte Mode

DCI

DATA[15:0]

FRAME

Q0N0

I1N3

I1N2

I1N1

I1N0

Q1N3

Q1N2

Q1N1

Q1N0

Q2N3

Figure 43. Timing Diagram for Nibble Mode

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