LAN9303 datasheet(29/366 Pages) SMSC

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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

SMSC LAN9303/LAN9303i

Revision 1.3 (08-27-09)

DATASHEET

Port 0 MII

Output Data 0

P0_OUTD0

MII MAC Mode: This pin is the transmit data 0 bit

from the switch to the external PHY.

MII PHY Mode: This pin is the receive data 0 bit

from the switch to the external MAC. The output

driver is disabled when the Isolate (VPHY_ISO) bit

is set in the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL).

RMII PHY Mode: This pin is the receive data 0 bit

from the switch to the external MAC. The output

driver is disabled when the Isolate (VPHY_ISO) bit

is set in the Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL).

Port 0 Mode[0]

Configuration

Strap

P0_MODE0

(PU)

Note 3.5

This strap configures the mode for Port 0. See

Note 3.4.

The P0_MODE[2:0] configuration strap encoding is

as follows:

000 = MII MAC mode

001 = MII PHY mode

010 = MII PHY mode 200 Mbps 12 ma clock output

011 = MII PHY mode 200 Mbps 16 ma clock output

100 = RMII PHY mode clock is 12 ma output

101 = RMII PHY mode clock is 16 ma output

110 = RMII PHY mode clock is input

111 = RESERVED

Port 0 MII

Output Data

Valid

P0_OUTDV

MII MAC Mode: This pin is the TX_EN signal to the

external PHY and indicates valid data on

P0_OUTD[3:0].

MII PHY Mode: This pin is the RX_DV signal to the

external MAC. The output driver is disabled when

the Isolate (VPHY_ISO) bit is set in the Virtual PHY

Basic Control Register (VPHY_BASIC_CTRL).

RMII PHY Mode: This pin is the CRS_DV signal to

the external MAC. The output driver is disabled

when the Isolate (VPHY_ISO) bit is set in the

Virtual PHY Basic Control Register

(VPHY_BASIC_CTRL).

Table 3.4 Port 0 MII/RMII Pins (continued)

NUM

PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

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