LAN9303 datasheet(44/366 Pages) SMSC

44 / 366 page

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

Revision 1.3 (08-27-09)

SMSC LAN9303/LAN9303i

DATASHEET

A nRST pin reset typically takes approximately 760uS, plus an additional 91uS per byte of data loaded

from the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in

approximately 6.0 seconds.

Note: The nRST pin is pulled-high internally. If unused, this signal can be left unconnected. Do not

rely on internal pull-up resistors to drive signals external to the device.

Please refer to Section Table 3.7, "Miscellaneous Pins," on page 38 for a description of the nRST pin.

4.2.2

Multi-Module Resets

Multi-module resets activate multiple internal resets, but do not reset the entire chip. Configuration

straps are not latched upon multi-module resets. A multi-module reset is initiated by assertion of the

following:

Digital Reset (DIGITAL_RST)

Multi-module reset/configuration completion can be determined by first polling the Byte Order Test

Once the returned data is the correct byte ordering value, the serial interface resets have completed.

The completion of the entire chip-level reset must then be determined by polling the Device Ready

(READY) bit of the Hardware Configuration Register (HW_CFG) until it is set. When set, the Device

Ready (READY) bit indicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG), Byte Order Test Register

(BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal resources is

forbidden while the Device Ready (READY) bit is cleared. Writes to any address are invalid until the

Device Ready (READY) bit is set.

Note: The digital reset does not reset register bits designated as NASR.

4.2.2.1

Digital Reset (DIGITAL_RST)

A digital reset is performed by setting the Digital Reset (DIGITAL_RST) bit of the Reset Control

PHY, Port 2 PHY, and Virtual PHY). The EEPROM Loader will automatically run following this reset.

Configuration straps are not latched as a result of a digital reset.

A digital reset typically takes approximately 760uS, plus an additional 91uS per byte of data loaded

from the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in

approximately 6.0 seconds.

4.2.3

Single-Module Resets

A single-module reset will reset only the specified module. Single-module resets do not latch the

configuration straps or initiate the EEPROM Loader. A single-module reset is initiated by assertion of

the following:

Port 2 PHY Reset

Port 1 PHY Reset

Virtual PHY Reset

4.2.3.1

Port 2 PHY Reset

A Port 2 PHY reset is performed by setting the Port 2 PHY Reset (PHY2_RST) bit of the Reset Control

(PHY_BASIC_CONTROL_x). Upon completion of the Port 2 PHY reset, the Port 2 PHY Reset

(PHY2_RST) and Reset (PHY_RST) bits are automatically cleared. No other modules of the device

are affected by this reset.

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