LAN9303 datasheet(67/366 Pages) SMSC

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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

SMSC LAN9303/LAN9303i

Revision 1.3 (08-27-09)

DATASHEET

Total multicast packets (Section 13.4.2.37, on page 263)

Total packets with a late collision (Section 13.4.2.38, on page 264)

Total packets with excessive collisions (Section 13.4.2.39, on page 265)

Total packets with a single collision (Section 13.4.2.40, on page 266)

Total packets with multiple collisions (Section 13.4.2.41, on page 267)

Total collision count (Section 13.4.2.42, on page 268)

6.4

Switch Engine (SWE)

The Switch Engine (SWE) is a VLAN layer 2 (link layer) switching engine supporting 3 ports. The SWE

supports the following types of frame formats: untagged frames, VLAN tagged frames, and priority

tagged frames. The SWE supports both the 802.3 and Ethernet II frame formats.

The SWE provides the control for all forwarding/filtering rules. It handles the address learning and

aging, and the destination port resolution based upon the MAC address and VLAN of the packet. The

SWE implements the standard bridge port states for spanning tree and provides packet metering for

input rate control. It also implements port mirroring, broadcast throttling, and multicast pruning and

filtering. Packet priorities are supported based on the IPv4 TOS bits and IPv6 Traffic Class bits using

a DIFFSERV Table mapping, the non-DIFFSERV mapped IPv4 precedence bits, VLAN priority using

a per port Priority Regeneration Table, DA based static priority, and Traffic Class mapping to one of 4

QoS transmit priority queues.

The following sections detail the various features of the Switch Engine.

6.4.1

MAC Address Lookup Table

The Address Logic Resolution (ALR) maintains a 512 entry MAC Address Table. The ALR searches

the table for the destination MAC address. If the search finds a match, the associated data is returned

indicating the destination port or ports, whether to filter the packet, the packet’s priority (used if

enabled), and whether to override the ingress and egress spanning tree port state. Figure 6.3 displays

the ALR table entry structure. Refer to the Switch Engine ALR Write Data 0 Register

(SWE_ALR_WR_DAT_0) and Switch Engine ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) for

detailed descriptions of these bits.

Figure 6.3 ALR Table Entry Structure

Age /

Override

Valid

Static

Filter

Priority

Port

MAC Address

...

Bit

Priority

Enable

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