LAN9303 datasheet(43/366 Pages) SMSC

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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

SMSC LAN9303/LAN9303i

Revision 1.3 (08-27-09)

DATASHEET

4.2.1

Chip-Level Resets

A chip-level reset event activates all internal resets, effectively resetting the entire device. Configuration

straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A chip-level reset

is initiated by assertion of any of the following input events:

Power-On Reset (POR)

nRST Pin Reset

Chip-level reset/configuration completion can be determined by first polling the Byte Order Test

Once the returned data is the correct byte ordering value, the serial interface resets have completed.

The completion of the entire chip-level reset must then be determined by polling the Device Ready

(READY) bit of the Hardware Configuration Register (HW_CFG) until it is set. When set, the Device

Ready (READY) bit indicates that the reset has completed and the device is ready to be accessed.

With the exception of the Hardware Configuration Register (HW_CFG), Byte Order Test Register

(BYTE_TEST), and Reset Control Register (RESET_CTL), read access to any internal resources is

forbidden while the Device Ready (READY) bit is cleared. Writes to any address are invalid until the

Device Ready (READY) bit is set.

4.2.1.1

Power-On Reset (POR)

A power-on reset occurs whenever power is initially applied to the device, or if the power is removed

and reapplied to the device. This event resets all circuitry within the device. Configuration straps are

latched, and the EEPROM Loader is run as a result of this reset.

A POR reset typically takes approximately 23mS, plus an additional 91uS per byte of data loaded from

the EEPROM via the EEPROM Loader. A full EEPROM load of 64KB will complete in approximately

6.0 seconds.

4.2.1.2

nRST Pin Reset

Driving the nRST input pin low initiates a chip-level reset. This event resets all circuitry within the

device. Use of this reset input is optional, but when used, it must be driven for the period of time

specified in Section 14.5.2, "Reset and Configuration Strap Timing," on page 351. Configuration straps

are latched, and the EEPROM Loader is run as a result of this reset.

Table 4.1 Reset Sources and Affected Device Circuitry

RESET SOURCE

POR

XXXXX

XXXXXX

nRST Pin

XXXXX

XXXXXX

Digital Reset

XXX

XXXX

Port 2 PHY

Port 1 PHY

Virtual PHY

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