ATmega32U2 datasheet(84/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

13. External Interrupts

13.1

Overview

The External Interrupts are triggered by the INT[7:0] pin or any of the PCINT[12:0] pins. Observe

that, if enabled, the interrupts will trigger even if the INT[7:0] or PCINT[12:0] pins are configured

as outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. PCMSK0 Reg-

ister control which pins contribute to the pin change interrupts. The Pin change interrupt PCI1

will trigger if any enabled PCINT[12:8] pin toggles. PCMSK1 Register control which pins contrib-

ute to the pin change interrupts. Pin change interrupts on PCINT[12:0] are detected

asynchronously. This implies that these interrupts can be used for waking the part also from

sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up

as indicated in the specification for the External Interrupt Control Registers – EICRA (INT[3:0])

and EICRB (INT[7:4]). When the external interrupt is enabled and is configured as level trig-

gered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or

rising edge interrupts on INT[7:4] requires the presence of an I/O clock, described in “System

Clock and Clock Options” on page 26. Low level interrupts and the edge interrupt on INT[3:0] are

detected asynchronously. This implies that these interrupts can be used for waking the part also

from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle

mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in “System Clock and Clock Options” on page 26.

13.2

13.2.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3:0 Sense Control Bits

The External Interrupts 3:0 are activated by the external pins INT[3:0] if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 13-1. Edges on INT[3:0] are registered asynchro-

nously. Pulses on INT[3:0] pins wider than the minimum pulse width given in “External Interrupts

Characteristics” on page 269 will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until the com-

pletion of the currently executing instruction to generate an interrupt. If enabled, a level triggered

interrupt will generate an interrupt request as long as the pin is held low. When changing the

ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its

Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn

Bit

76543210

(0x69)

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

EICRA

Read/Write

R/W

Initial Value

00000000

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