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ATmega32U2 Datasheet(PDF) 86 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 86 Page - ATMEL Corporation |
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86 / 314 page  86 7799B–AVR–07/09 ATmega8U2/16U2/32U2 13.2.3 EIMSK – External Interrupt Mask Register • Bits 7:0 – INT[7:0]: External Interrupt Request 7:0 Enable When an INT[7:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is acti- vated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. 13.2.4 EIFR – External Interrupt Flag Register • Bits 7:0 – INTF[7:0]: External Interrupt Flags 7:0 When an edge or logic change on the INT[7:0] pin triggers an interrupt request, INTF[7:0] becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT[7:0] in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT[7:0] are configured as level interrupt. Note that when entering sleep mode with the INT[3:0] interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF[3:0] flags. See “Digital Input Enable and Sleep Modes” on page 71 for more information. 13.2.5 PCICR – Pin Change Interrupt Control Register • Bit 1:0 – PCIE[1:0]: Pin Change Interrupt Enable 1:0 When the PCIE1/0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), Pin Change interrupt 1/0 is enabled. Any change on any enabled PCINT[12:8]/[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1/0 Interrupt Vector. PCINT[12:8]/[7:0] pins are enabled individually by the PCMSK1/0 Register. 13.2.6 PCIFR – Pin Change Interrupt Flag Register Bit 76543210 0x1D (0x3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 76543210 0x1C (0x3C) INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0 EIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 00000000 Bit 7 6543 210 (0x68) - - – – – – PCIE1 PCIE0 PCICR Read/Write RRRR RR R/W R/W Initial Value 0 0000 000 Bit 7 6543 210 0x1B (0x3B) - - – – – – PCIF1 PCIF0 PCIFR Read/Write RRRR RR R/W R/W Initial Value 0 0000 000 |
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