ATmega32U2 datasheet(27/314 Pages) ATMEL

27 / 314 page

7799B–AVR–07/09

ATmega8U2/16U2/32U2

8.1.4

USB Clock – clk

USB

The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL

running at 48 MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register

should be programmed by software to generate a 8 MHz clock on the PLL input.

8.2

Clock Switch

In the ATmega8U2/16U2/32U2 product, the Clock Multiplexer and the System Clock Prescaler

can be modified by software.

8.2.1

Exemple of use

The modification can occur when the device enters in USB Suspend mode. It then switches from

External Clock to Calibrated RC Oscillator in order to reduce consumption. In such a configura-

tion, the External Clock is disabled.

The firmware can use the watchdog timer to be woken-up from power-down in order to check if

there is an event on the application.

If an event occurs on the application or if the USB controller signals a non-idle state on the USB

line (Resume for example), the firmware switches the Clock Multiplexer from the Calibrated RC

Oscillator to the External Clock.

Figure 8-2.

Example of clock switching with wake-up from USB Host

USB

CPU Clock

External

Oscillator

RC oscillator

Ext

non-Idle

Idle

(Suspend)

non-Idle

3ms

resume

1 Resume from Host

Watchdog wake-up

from power-down

ATmega32U2 Datasheet(PDF) 27 Page - ATMEL Corporation