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ATmega32U2 Datasheet(PDF) 42 Page - ATMEL Corporation |
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ATmega32U2 Datasheet(HTML) 42 Page - ATMEL Corporation |
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42 / 314 page ![]() 42 7799B–AVR–07/09 ATmega8U2/16U2/32U2 9. Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. 9.2 Sleep Modes Figure 8-1 on page 26 presents the different clock systems in the ATmega8U2/16U2/32U2, and their distribution. The figure is helpful in selecting an appropriate sleep mode. shows the differ- ent sleep modes and their wake up sources. Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2. For INT[7:4], only level interrupt. 3. Asynchronous USB interrupt is WAKEUPI only. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, Power-down, Power-save, Standby or Extended standby) will be acti- vated by the SLEEP instruction. See Table 9-2 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 9.3 Idle Mode When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, Timer/Counters, Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators Wake-up Sources Sleep Mode Idle X X XXX XXX Power-down X(2) XX Power-save X(2) XX Standby(1) XX(2) XX Extended Standby XX(2) XX |
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