ATmega32U2 datasheet(85/314 Pages) ATMEL

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7799B–AVR–07/09

ATmega8U2/16U2/32U2

interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the

EIFR Register before the interrupt is re-enabled.

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

13.2.2

EICRB – External Interrupt Control Register B

• Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7:4 Sense Control Bits

The External Interrupts [7:4] are activated by the external pins INT[7:4] if the SREG I-flag and

the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins

that activate the interrupts are defined in Table 13-2. The value on the INT[7:4] pins are sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one

clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-

rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL

divider is enabled. If low level interrupt is selected, the low level must be held until the comple-

tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered

interrupt will generate an interrupt request as long as the pin is held low.

Note:

1. n = 7, 6, 5 or 4.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Table 13-1.

Interrupt Sense Control

(1)

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any edge of INTn generates asynchronously an interrupt request.

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Bit

76543210

(0x6A)

ISC71ISC70

ISC61ISC60

ISC51ISC50

ISC41ISC40

EICRB

Read/Write

R/W

Initial Value

00000000

Table 13-2.

Interrupt Sense Control

(1)

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any logical change on INTn generates an interrupt request

The falling edge between two samples of INTn generates an interrupt request.

The rising edge between two samples of INTn generates an interrupt request.

ATmega32U2 Datasheet(PDF) 85 Page - ATMEL Corporation

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