ATmega32U2 datasheet(89/314 Pages) ATMEL

89 / 314 page

7799B–AVR–07/09

ATmega8U2/16U2/32U2

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 14-2. Prescaler for synchronous Timer/Counters

14.5

14.5.1

GTCCR – General Timer/Counter Control Register

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

PSR10

Clear

clk

I/O

Synchronization

TIMER/COUNTERn CLOCK SOURCE

clk

TIMER/COUNTERn CLOCK SOURCE

clk

CSn0

CSn1

CSn2

CSn0

CSn1

CSn2

Bit

0x23 (0x43)

TSM

–

PSRSYNC

GTCCR

Read/Write

R/W

Initial Value

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